Understanding and Using Adapt812 Expanded Modes

Immediately following reset in one of the expanded modes, CSP0 is active and all high-order address lines are high.  Therefore the section of program memory that is visible to the CPU from 0x8000 - 0xffff is actually the two uppermost 16K blocks of Flash .  After the reset vector is fetched, the initialization code is executed.  If that code enables the Program Window, the CPU's address space from 0x8000 - 0xbfff now becomes paged memory and the PPAGE defaults to 0, so the memory being addressed in that range is no longer the second-last 16K page of physical memory.  Instead it is now the first 16K block of physical memory.  That is why the initialization code cannot reside at 0x8000.  The area of memory from 0xc000 - 0xffff however, is still absolute (ie non-paged), so it is still the last 16K block of program memory, and is therefore a "safe place" to put init code and ISRs.

The user startup code, vectors, and interrupt service routines must all be in fixed (ie. non-banked) area of program memory.  That means all s1 records should reference memory from 0xc000 to 0xffff only.  S2 records reference paged memory, so an address of 0x000000 in an S2 record refers to address 0 in Page 0 of the Program Page window at 0x8000.  It is up to the user to initialize the appropriate 812 registers for expanded memory use, in the startup code.  The relevant registers are:

MXAR    to turn on high-order address lines (A16 for 128K Program Memory; A16,A17, & A18 for 512K device)
PEAR    to enable R/W for external RAM access (in a wide-mode system, LSTRB must also be enabled to permit byte-wise RAM access)
CSCTL0    to enable CSD and CSP0 for external memory access
WINDEF    to enable the Program and Data pages (and EPAGE, if applicable)

How the Flash Utilities Work

Expanded Narrow Mode systems (eg. Adapt812DX, Adapt812DXLT, and Adapt812 + MX1) use MXFlash, while Expanded Wide Mode systems (eg. Adapt812MAX and Adapt812 + MX2) use MAXFlash.  The main difference is that MXFlash programs Flash one byte at a time, while MAXFlash programs Flash one word at a time, on even address boundaries.

Both utilities process an .s19 file, extracting address, byte-count, and data information from the s-record.  Note that an .s19 file may contain s1, s2, and s9 records.

When an s1 record is encountered, it's destination address is considered absolute.  However, if the address is between 0xC000 and 0xFFFF, the location has to be programmed via the page window, since the 4K block of EEPROM is active from $F000 - $FFFF, making direct access in that range impossible.  So the utility translates the address into an offset into the Page window by subtracting 0x4000, and sets PPAGE to "LASTPAGE", where LASTPAGE is determined by reading the Flash device's configuration code.  For a 128K device, LASTPAGE = 0x07, while for a 512K device LASTPAGE = 0x1F.

If an s2 record is encountered, the address is divided by 16K to determine what destination page it falls in, and the remainder is added to 0x8000 to create a corresponding address within the 16K Program Window (at 0x8000).  With PPAGE set accordingly, the data is now programmed into Flash at the destination address.  For more on how s2 records are interpreted in a 68HC12 paged memory model, see Motorola's DBug12 document at  http://www.technologicalarts.com/myfiles/data/db12rg.pdf

The latest versions of the Flash utilities can be downloaded here:

Special Note for Adapt812DXLT (Rev. 0) Users:
System address line A19 was included in the decoding logic, along with CSD, so that two 512K RAM devices can be used in a system (eg. use an 812MX1 512K board with an Adapt812DX512 board), allowing for the full 1MB of possible data space.  Unfortunately, this logic was held over when revision 0 of Adapt812DXLT was designed.  There is no advantage to having this decoding logic, since the data space comprises a single 32K RAM device.  The impact, however, is that A19 must be high to select the data RAM.  While it would be possible to allow for this in software, a simple hardware workaround is recommended, in order to maintain software compatibilty with the next revision of the board (which will have this circuitry removed).  You should modify the board so that pin 2 of JB3 is tied high.
 
 
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